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19-4767; Rev 2; 1/99
ANUAL N KIT M LUATIO ATA SHEET EVA WS D FOLLO
+3.3V, 2.488Gbps, SDH/SONET 1:16 Deserializer with LVDS Outputs
Features
o Single +3.3V Supply o 2.488Gbps Serial to 155Mbps Parallel Conversion o 660mW Operating Power o LVDS Data Outputs and Synchronization Inputs o Self-Biasing PECL Inputs Ease AC Coupling o Synchronization Inputs for Data Realignment and Reframing
General Description
The MAX3885 deserializer is ideal for converting 2.488Gbps serial data to 16-bit wide, 155Mbps parallel data in SDH/SONET applications. Operating from a single +3.3V supply, this device accepts PECL serial clock and data inputs, and delivers low-voltage differential-signal (LVDS) clock and data outputs for interfacing with high-speed digital circuitry. It also provides an LVDS synchronization input that enables data realignment and reframing. The MAX3885 is available in the extended temperature range (-40C to +85C) in a 64pin TQFP package.
MAX3885
Applications
2.488Gbps SDH/SONET Transmission Systems Add/Drop Multiplexers Digital Cross Connects
PART MAX3885ECB
Ordering Information
TEMP. RANGE -40C to +85C PIN-PACKAGE 64 TQFP
Pin Configuration appears at end of data sheet.
Typical Operating Circuit
VCC = +3.3V VCC = +3.3V VCC = +3.3V 133 133 SD+ VCC PD15+ 100* PD15SD86.6 SERIAL DATA INPUTS DATA AND CLOCK RECOVERY 133 86.6
* * *
MAX3875
OVERHEAD TERMINATION
MAX3885
PD0+
VCC = +3.3V PD0133 SCLK+ SCLK86.6 86.6 PCLKSYNC+ SYNCGND PCLK+
100*
100*
*REQUIRED ONLY IF OVERHEAD CIRCUIT DOES NOT INCLUDE INTERNAL INPUT TERMINATION. THIS SYMBOL REPRESENTS A TRANSMISSION LINE OF CHARACTERISTIC IMPEDANCE Z0 = 50.
________________________________________________________________ Maxim Integrated Products
1
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+3.3V, 2.488Gbps, SDH/SONET 1:16 Deserializer with LVDS Outputs MAX3885
ABSOLUTE MAXIMUM RATINGS
Positive Supply Voltage (VCC)...............................-0.5V to +7.0V Input Voltage Level (all inputs)...................-0.5V to (VCC + 0.5V) Output Current LVDS outputs .............................................10mA Continuous Power Dissipation (TA = +85C) TQFP (derate 24mW/C above +85C) .......................1000mW Operating Temperature Range ...........................-40C to +85C Storage Temperature Range .............................-60C to +160C Lead Temperature (soldering, 10sec) .............................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
(VCC = +3.0V to +3.6V, differential loads = 100 1%, TA = -40C to +85C, unless otherwise noted. Typical values are at VCC = +3.3V, TA = +25C.) PARAMETER SYMBOL CONDITIONS UNITS MIN TYP MAX Supply Current PECL INPUTS (SD+/-, SCLK+/-) Input High Voltage Input Low Voltage Input High Current Input Low Current Input Voltage Range Differential Input Threshold Threshold Hysteresis Differential Input Resistance Output High Voltage Output Low Voltage Differential Output Voltage Change in Magnitude of Differential Output Voltage for Complementary States Output Offset Voltage Change in Magnitude of Output Offset Voltage for Complementary States Single-Ended Output Resistance Change in Magnitude of SingleEnded Output Resistance for Complementary Outputs VIH VIL IIH IIL VI VIDTH VHYST RIN VOH VOL V OD V OD VOS VOS RO RO 40 95 2.5 1.125 0.925 Figure 1 250 400 25 1.275 25 140 10 85 VIN = VIH(MAX) VIN = VIL(MIN) Differential input voltage = 100mV Common-mode voltage = 50mV VCC - 1.16 VCC - 1.81 -900 -900 0 -100 78 100 115 1.475 VCC - 0.88 VCC - 1.48 900 900 2.4 100 V V A A V mV mV V V mV mV V mV % ICC 200 280 mA
LVDS INPUTS AND OUTPUTS (SYNC+/-, PCLK+/-, PD_+/-)
AC ELECTRICAL CHARACTERISTICS
(VCC = +3.0V to +3.6V, differential loads = 100 1%, TA = -40C to +85C, unless otherwise noted. Typical values are at VCC = +3.3V, TA = +25C.) (Note 1, Figure 4) PARAMETER Maximum Serial Clock Frequency Serial Data Setup Time Serial Data Hold Time Parallel Clock-to-Data Output Delay SYMBOL fSCLK tSU tH tCLK-Q CONDITIONS MIN 2.488 100 100 200 450 900 TYP MAX UNITS GHz ps ps ps
Note 1: AC Characteristics guaranteed by design and characterization. 2 _______________________________________________________________________________________
+3.3V, 2.488Gbps, SDH/SONET 1:16 Deserializer with LVDS Outputs
Typical Operating Characteristics
(VCC = +3.3V, TA = +25C, unless otherwise noted.)
MAX3885
MAXIMUM SERIAL CLOCK FREQUENCY vs. TEMPERATURE
MAX3885-01
SERIAL DATA-SETUP TIME vs. TEMPERATURE
MAX3885-02
SERIAL DATA-HOLD TIME vs. TEMPERATURE
MAX3885-03
4.4 MAX SERIAL CLOCK FREQUENCY (GHz) VCC = 3.6V 4.3 VCC = 3V 4.2
100 SERIAL DATA-SETUP TIME (ps)
0
80
SERIAL DATA-HOLD TIME (ps)
-20
60
-40
40
-60
4.1
20
-80
4.0 -50 -25 0 25 50 75 100 TEMPERATURE (C)
0 -50 -25 0 25 50 75 100 TEMPERATURE (C)
-100 -50 -25 0 25 50 75 100 TEMPERATURE (C)
SUPPLY CURRENT vs. TEMPERATURE
MAX3885-04
PARALLEL CLOCK TO DATA OUTPUT PROPAGATION DELAY vs. TEMPERATURE
PCLK TO DATA OUTPUT PROPAGATION DELAY (ps)
MAX3885-05
300
700
SUPPLY CURRENT (mA)
250 VCC = 3.6V 200 VCC = 3V
600
500
400
150
300
100 -50 -25 0 25 50 75 100 TEMPERATURE (C)
200 -50 -25 0 25 50 75 100 TEMPERATURE (C)
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+3.3V, 2.488Gbps, SDH/SONET 1:16 Deserializer with LVDS Outputs MAX3885
Pin Description
PIN 1, 2, 8, 16, 17, 24, 32, 33, 41, 48, 49, 57, 64 3, 5, 7, 9, 11, 13, 25, 34, 42, 47, 56 4 6 10 12 14 15 18 19 20, 22, 26, 28, 30, 35, 37, 39, 43, 45, 50, 52, 54, 58, 60, 62 21, 23, 27, 29, 31, 36, 38, 40, 44, 46, 51, 53, 55, 59, 61, 63 NAME GND Ground FUNCTION
VCC
+3.3V Supply Voltage Serial Data Noninverting PECL Input. Data is clocked on the SCLK signal's positive transition. Serial Data Inverting PECL Input. Data is clocked on the SCLK signal's positive transition. Serial Clock Noninverting PECL Input Serial Clock Inverting PECL Input Synchronizing Pulse Inverting LVDS Input. Pulse the SYNC signal high for at least four SCLK periods to shift the data alignment by dropping one bit. Synchronizing Pulse Noninverting LVDS Input. Pulse the SYNC signal high for at least four SCLK periods to shift the data alignment by dropping one bit. Parallel Clock Inverting LVDS Output Parallel Clock Noninverting LVDS Output Parallel Data Inverting LVDS Outputs. Data is updated on the negative transition of the PCLK signal.
SD+ SDSCLK+ SCLKSYNCSYNC+ PCLKPCLK+
PD0- to PD15-
PD0+ to PD15+
Parallel Data Noninverting LVDS Outputs. Data is updated on the negative transition of the PCLK signal.
PD+ D PDVPDSINGLE-ENDED OUTPUT VPD+ VOH RL = 100 V VOD
|VOD|
VOS VOL
VPD+ - VPDDIFFERENTIAL OUTPUT 0V (DIFF.) 0V
+VOD VOD, P - P = VPD+ - VPD-VOD
Figure 1. Driver Output Levels
4 _______________________________________________________________________________________
+3.3V, 2.488Gbps, SDH/SONET 1:16 Deserializer with LVDS Outputs
Detailed Description
The MAX3885 deserializer uses a 16-bit shift register, 16-bit parallel output register, 4-bit counter, PECL input buffers, and low-voltage differential-signal (LVDS) input/output buffers to convert 2.488Gbps serial data to 16-bit wide, 155Mbps parallel data (Figure 2). The input shift register continuously clocks incoming data on the positive transition of the serial clock (SCLK) input signal. The 4-bit counter generates a parallel-output clock (PCLK) by dividing the serial-clock frequency by 16. The PCLK signal clocks the parallel-output register. During normal operation, the counter divides the SCLK frequency by 16, causing the output register to latch every 16 bits of incoming serial data. The synchronization inputs (SYNC+, SYNC-) realign and reframe data. When the SYNC signal is pulsed high for at least four SCLK cycles, the parallel output data is delayed by one SCLK cycle. This realignment is guaranteed to occur within two complete PCLK cycles of the SYNC signal's positive transition. As a result, the first incoming bit of data during that PCLK cycle is dropped, shifting the alignment between PCLK and data by one bit. See Figure 3 for the timing diagram and Figure 4 for the timing parameters diagram.
MAX3885
SD+ SDSCLK+ SCLKPECL PECL 16-BIT SHIFT REGISTER 16-BIT PARALLEL OUTPUT REGISTER LVDS
PD15+ PD15-
PD1+ LVDS
MAX3885
PD1PD0+
Low-Voltage Differential-Signal (LVDS) Inputs and Outputs
The MAX3885 features LVDS inputs and outputs for interfacing with high-speed digital circuitry. The LVDS standard is based on the IEEE 1596.3 LVDS specification. This technology uses 500mVp-p to 800mVp-p differential low-voltage swings to achieve fast transition times, minimize power dissipation, and improve noise immunity. The parallel clock and data LVDS outputs (PCLK+, PCLK-, PD_+, PD_-) require 100 differential
LVDS
PD0PCLK+
SYNC+ SYNC100 LVDS
4-BIT COUNTER
LVDS
PCLK-
Figure 2. Functional Diagram
D15
D14
D13 SCLK SD SYNC
PCLK
(LSB) PD0
D0
D16
D32
D48
D65
PD1 * * * (MSB) PD15 TRANSMITTED FIRST
D1
D17
D33
D49 ONE BIT HAS SLIPPED IN THIS TIME SLICE
D66
D15
D31
D47
D64
D80
Figure 3. Timing Diagram
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+3.3V, 2.488Gbps, SDH/SONET 1:16 Deserializer with LVDS Outputs MAX3885
tSCLK = 1 / fSCLK SCLK tSU SD tH
PCLK tCLK-Q PD0-PD15
NOTE: SIGNALS SHOWN ARE DIFFERENTIAL. FOR EXAMPLE, SCLK = (SCLK+) - (SCLK-).
Figure 4. Timing Parameters
DC termination between the inverting and noninverting outputs for proper operation. Do not terminate these outputs to ground. The synchronization LVDS inputs (SYNC+, SYNC-) are internally terminated with 100 differential input resistance and, therefore, do not require external termination.
THEVENIN-EQUIVALENT TERMINATION +3.3V 133 ZO = 50 133
MAX3885
PECL INPUTS
PECL Inputs
Because of the self-biasing resistor networks, the serial data and clock PECL inputs (SD+, SD-, SCLK+, SCLK-) require 53 termination to VCC - 2V when interfacing with a PECL source (see Alternative PECL Input Termination). This results in an equivalent input resistance of 50.
ZO = 50
86.6
86.6
Applications Information
Alternative PECL Input Termination
Figure 5 shows alternative PECL input-termination methods. Use Thevenin-equivalent termination when a VCC - 2V termination voltage is not available. When interfacing with an ECL-output device, the MAX3885's internal self-biasing allows easy ECL AC-coupling termination.
ECL AC-COUPLING TERMINATION
ZO = 50
MAX3885
53 PECL INPUTS
Layout Techniques
For best performance, use good high-frequency layout techniques. Filter voltage supplies and keep ground connections short. Use multiple vias where possible. Also, use controlled impedance transmission lines to interface with the MAX3885 high-speed inputs and outputs.
ZO = 50
-2V
53 -2V
Figure 5. Alternative PECL Input Termination
6 _______________________________________________________________________________________
+3.3V, 2.488Gbps, SDH/SONET 1:16 Deserializer with LVDS Outputs
Pin Configuration
PD9+ PD8+ PD7+ PD6+ PD5+ PD9PD8PD7PD6PD5GND GND GND
MAX3885
VCC
VCC
TOP VIEW
48
47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
GND 49 PD10- 50 PD10+ 51 PD11- 52 PD11+ 53 PD12- 54 PD12+ 55 VCC 56 GND 57 PD13- 58 PD13+ 59 PD14- 60 PD14+ 61 PD15- 62 PD15+ 63 GND 64
VCC
32 GND 31 PD4+ 30 PD429 PD3+ 28 PD327 PD2+ 26 PD225 VCC
MAX3885
24 GND 23 PD1+ 22 PD121 PD0+ 20 PD019 PCLK+ 18 PCLK17 GND
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
SYNC-
SCLK-
SYNC+
SCLK+
GND
GND
GND
SD-
TQFP
___________________Chip Information
TRANSISTOR COUNT: 2820
_______________________________________________________________________________________
GND
SD+
VCC
VCC
VCC
VCC
VCC
VCC
7
+3.3V, 2.488Gbps, SDH/SONET 1:16 Deserializer with LVDS Outputs MAX3885
Package Information
TQFPPO.EPS
8
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